Shallow trench isolation (STI) voids are problematic in finFETs and are one of the top yield detractors. In a standard finFET design, gate material such as hafnium (Hf) and titanium (Ti) can be detected at a void located between a source/drain (S/D) material and the gate which can lead to a trench silicide-gate (TS-PC) short. As shown in FIG. 1A, a gate 101 and fin 103 are illustrated in a conventional finFET. Inner spacer 105 and outer spacer 107 are disposed at sides of the gate 101 and over the fin 103. FIG. 1B is a sectional view along arrow A. In the illustration of FIG. 1B, a failure can occur at a void within circle 109 which is located adjacent to the fin 103.
Bi-layer spacers on sides of the gate 101 and the fin 193 are used to prevent voids formed at weak points. Inner spacer 105 can include a dielectric material such a silicon nitride (SiN), and the outer spacer 107 can include a dielectric material such as an oxide. The outer spacer 107 is more prone to etching. Inner spacer 105 has a lower carbon percentage (C %) to achieve a lower dielectric constant to increase circuit speed. The outer spacer 107 has a high C % for improved resistance to various cleaning processes that result in spacer material loss.
In finFET technology, there are multiple processes during junction cleaning and replacement metal gate (RMG) cleaning, such as ashing, remote plasma assisted dry etch processing, or other cleaning processes, that can attack low-k dielectric materials such as the inner spacer 105. The inner spacer 105 is generally considered as a “weaker” material that has a much faster etch rate than the outer spacer 107. For example, the etch rate of the inner spacer 105 is 6× higher when a dilute hydrofluoric (DHF) acid etchant is used.
As shown in FIG. 2A, the gate 101 is disposed over the fin 103, with inner spacer 105 and outer spacer 107 disposed around the gate 101. During the junction cleaning, as shown in FIG. 2A, a void within circle 201 is formed at a weak point of the inner spacer 105. Moreover, during RMG processing following the removal of the polysilicon gate material, as shown in FIG. 2B, void 201 within circle 201 is also present. The challenge faced by the bi-layer spacer scheme is that the inner spacer 105 tends to be the weak point during cleaning and etching processes which results in a void that links the gate 101 and a S/D region.
A need therefore exists for methodology that provides a spacer with a low dielectric constant but a higher resistance to cleaning processes, and improves the performance of resulting devices.